This invention concerns an electronic totalizing circuit, more specifically a counter to receive counting pulses, so constructed that the counter contents are stored in a non-volatile memory, so that the contents will not be lost when the electric energy feeding the counter is switched off.
A counter of this kind can be formed of synchronous flipflops, provided with safeguard circuits: under normal operating conditions, these flipflops change status in relation to their input signals, under the control of a clock signal, while a safeguard signal protects the state of the flipflop in a non-volatile way, so that, when power has been cut, the flipflop can be reset in the memorized state, either automatically, or through a resetting signal.
FIG. 1 shows a specimen synchronous bistable flipflop with a safeguard circuit and with controlled resetting. This is a master/slave JK flipflop with two inputs J and K, clock inputs H and H* (where the asterisk indicates a signal complementary to a given signal), a forced clearance input R, and a resetting signal input CCR. The actual flipflop basically comprises four master flipflop transistors T.sub.1 to T.sub.4, and four slave flipflop transistors T.sub.5 to T.sub.8. The safeguard circuit basically comprises two MNOS (Metal/Nitride/Oxide/Semiconductor) transistors TM.sub.1 and TM.sub.2, which provide non-volatile storage for trapped electric charges, that make them either conducting or blocked.
Flipflop states are safeguarded by means of a safeguard control signal C.sub.S, which allows a higher writing voltage V.sub.e than the normal operating voltage V.sub.cc to be applied to the flipflop; simultaneously, the collectors of the MNOS transistors TM.sub.1 and TM.sub.2 are isolated from the supply line, by means of a low signal (0 volt), applied to the resetting input CCR. The emitters of TM.sub.1 and TM.sub.2, connected to the master flipflop outputs, are energized either to 0 volt or to the writing voltage V.sub.e, depending on the state of the flipflop.
Transistors TM.sub.1 and TM.sub.2 adopt a forced permanent conducting or blocked state, which depends directly on the time at which the control signal C.sub.s has been applied.
The flipflop state is also reset by means of the signal CCR in the high state, which connects the MNOS transistors TM.sub.1 and TM.sub.2 to the supply line, to force the master flipflop into a state connected to the state of blockage or conduction of these transistors. The flipflop then regains the state it possessed at the time of the safeguard operation.
The circuit in FIG. 1 is given only as an example, to illustrate the functioning of a bistable flipflop with a safeguard and resetting circuit. Other flipflops may be used, such as D instead of JK flipflops, or safeguard circuits with floating-base transistors, instead of MNOS transistors, and so on.
For certain counting purposes, it is necessary to store counter contents in a non-volatile memory, at all times, for instance to meter the duration or number of operating cycles of an appliance which functions only intermittently, with the power supply to it (and thus to the counter) switched off after each use. Under these circumstances, a safeguard stage must be included after every incrementation of the counter (in the following description, the word "incrementation" will be used in the widest sense of incrementation or decrementation, since the invention encompasses counters, discounters and reversible counters).
Now, MNOS or floating-base transistors, which are the basic components of safeguard circuits, can withstand only a limited number of writing cycles, after which they gradually deteriorate, and are no longer capable of trapping properly the electric charges which make them conducting or blocked. This results in a reduction in retention of stored data, and also in a risk of wrong resetting, because of changes in transistor blocking threshold voltages after a large number of writing cycles.
The maximum reliable number of cycles would appear to be 10.sup.5 to 10.sup.6 for MNOS devices, which rules out applications where the counter has to function for around this number of cycles.
In order to increase the maximum number of incrementations that the counter can accept while safeguarding its contents at every such incrementation, this invention proposes a counting unit comprising a loop of several flipflops, the outputs of which represent the contents of the counting unit in binary form, in a particular code in which no bit changes more than twice in the course of a complete counting cycle of the unit, and further comprising means of activating non-volatile memorization of flipflop output states, and a selection logic circuit connected to these activating means, to prohibit activating memorization of the state of flipflops that have not changed after an incrementation of the counting unit, and to enable activating memorization of the state of flipflops that have changed after such incrementation.
Consequently, instead of a counter constructed in the conventional way, with the flipflops arranged to count normally in pure binary code, or BCD ("binary coded decimal"), commonest for counters required to represent decimal numbers, this invention uses a different code, preferably the "Johnson code", which will be explained below, or a similar code, from the point of view of the reduced number of changes of each bit during a complete counting cycle. In addition, safeguarding at each incrementation is carried out only for flipflops that have changed status.
These two features, the small number of status changes of flipflops, and selection of flipflops whose contents need to be safeguarded after a status change, help to reduce the number of writing cycles performed by each flipflop, and thereby increase the overall useful life of the counter.
The term "counting unit" is used, since a counter may comprise several counting units, each corresponding to figures of different weights in the counting result; e.g. a four-digit decimal counter (0 to 9999) will comprise four cascade-connected counting units, constituting four counting decades. Each such decade has a complete cycle of ten successive incrementations. But it would be possible to have a counter displaying a four-digit hexadecimal result (0000 to FFFF); each counting unit would in this case perform a counting cycle of sixteen incrementations.
Basically, a counting unit, taken individually, should have several outputs (outputs from flipflops of the loop composing this unit), and these outputs should define, in the form of several bits, a one-digit numerical counting result (0 to 9 for a decade in decimal), in accordance with a special binary code in which each bit changes not more than twice during a cycle (0 to 9 in decimal).
The Johnson code is particularly suitable, since it complies with this condition, and, as will be seen below, allows an extremely simple combinative logic circuit to identify, after an incrementation at the counter, and therefore after every counting pulse, the flipflops which have to undergo a writing cycle (two flipflops for each counting pulse), depending on the state of flipflop outputs, and possibly on the existence of a general clearance signal for the counting unit or counter.